Digital video streams are typically encoded using one of many different encoding standards. For example, a digital video stream may be compressed for conversion into a data format that requires fewer bits. This compression can be lossless such that the original video stream can be recreated upon decoding or can be lossy such that an exact replica of the original video stream cannot be recreated, but where the decoding of the compressed data is more efficient. Once decoded, a video stream may require rotation for proper display. For example, a digital still image may be rotated ninety degrees to one side, and needs to be rotated to properly view the digital still image. Digital movies are also subject to the need for rotation.
Currently, a frame of a video stream cannot be rotated until the entire frame is decoded and is stored in a memory. This requires a second pass at the decoded data, at an additional cost in both memory and processing overhead.
Accordingly, current digital still image or digital movie rotation is not available until at least a frame is completely decoded and written to memory. Thus, what is needed is a video stream rotation engine that overcomes the limitations on the prior art. The new video stream rotation engine provide for rotating a video stream “on-the-fly,” before the video stream is written to memory.
Embodiments of the present invention provide a rotation engine for rotating a video stream “on-the-fly,” before the video stream is written to memory. Embodiments of the present invention are capable of rotating the video stream by rotating macro-blocks of a video stream as they are received and repositioning the macro-blocks within the frame based on the rotation. Embodiments of the present invention are capable of rotating video streams without requiring a second pass at the decoded frames by operating on macro-blocks at prior to writing the decoded macro-blocks to memory.
In one embodiment, the present invention provides a method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.
In one embodiment, the macro-block is stored within a memory for display. In one embodiment, the macro-block is a decoded macro-block. In one embodiment, a post-processing operation is performed on the decoded macro-block. In another embodiment, the video stream is decoded. In one embodiment, the degree of rotation is one of: ninety-degrees clockwise, ninety-degrees counter-clockwise, and one-hundred eighty degrees. In one embodiment, the rotation of the macro-block and the repositioning of the macro-block are performed prior to accessing a memory.
In another embodiment, the present invention provides a video decoder device including a video decoder and a rotation engine. The video decoder is configured for decoding a video stream. The rotation engine is configured for rotating a macro-block of a frame of the video stream according to a degree of rotation and for repositioning the macro-block to a new position within the frame, wherein the new position is based on the degree of rotation. In one embodiment, the video decoder device is implemented within an integrated circuit coupled to a printed circuit board, in which the printed circuit board is coupled to a connector for removably coupling the printed circuit board to a computer system.
In one embodiment, the video decoder device further includes a memory for storing the macro-block for display. In one embodiment, the video decoder device further includes filter for performing a post-processing operation on the macro-block. In one embodiment, the degree of rotation is one of: ninety-degrees clockwise, ninety-degrees counter-clockwise, and one-hundred eighty degrees. In one embodiment, the rotation engine is configured to rotate the macro-block and to reposition the macro-block within the frame prior to accessing a memory.
In one embodiment, the video decoder is a hardware multi-standard video decoder device including a command parser and a plurality of hardware decoding blocks. The command parser is configured for accessing the video stream and for identifying a video encoding standard used for encoding the video stream. The plurality of hardware decoding blocks is configured for performing operations associated with decoding the video stream, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards.